The present invention relates to a pair of complementary conductivity type transistors, and more particularly to such a pair that have about equal currents when changing logic states.
There is interest in using GaAs metal semiconductor field effect transistors (MESFETs) in logic circuits due to their higher speed and radiation resistance as compared to silicon (Si) FETs.
A typical logic gate has a depletion or enhancement mode (normally ON and OFF, respectively) driver FET and a load, such as a resistor or a depletion mode FET, coupled thereto. However, such a circuit consumes power when in the quiescent (non-switching) state. This limits the gate packing density when many such gates are formed in an integrated circuit (IC) due to heat dissipation limitations of the IC. It has been suggested in the article "p-Channel (AL,Ga) As/GaAs Modulation-Doped Logic Gates", by R. A. Kiehl et al., IEEE Electron Device Letters, Vol. EDL-5, No. 10, Oct. 1984, pp. 420-422, to use complementary conductivity type MESFETs in a logic gate so that the gate draws current only when changing states, and therefore consumes only a small amount of power. Thus a high packing density can be achieved. However, in such a circuit, the currents in the P-channel and N-channel FETs are not equal due to the difference in mobility of holes and electrons. This results in different values for the rise and fall times of an output logic pulse, especially when the output of the logic gate drives a capacitive load, such as another FET logic gate. In turn, a timing error in logic signals occurs, which can cause erroneous logic signals.
It is therefore desirable to provide a circuit that has low power requirements in order to achieve a high packing density and substantially equal, preferably as equal as possible, currents in complementary conductivity type transistors when changing states to avoid erroneous logic signals.